Digital logic and mixed signal hardmacros are normally developed for backend implementation in a lowest possible layer stack. A layer stack defines either a particular subset of physical layers or all of the physical layers in a technology available to a circuit designer. However, looking at a number of different possible layer stacks available for conventional technologies, a lot of unsupported layer stacks exist. In most cases, unsupported layer stacks have no rules available for handling by automatic place-and-route software tools.
All of the layers not used in a hardmacro are commonly completely blocked for top level automatic network routing. Route guides can prevent a network of a circuit, not included as an inherent part of the hardmacro, from being routed across any portion of the hardmacro. The completely blocked layers cause network paths to go around the hardmacro adding significant wire delay. A lot of routing space in the circuit is also lost and a lot of pseudo routing violations can appear. As such, automatic routing routines are negatively influenced by the blockages. Furthermore, conventional automated routing tools do not always pay attention to the route guides. Therefore, a high number of routing violations can be caused which slow down both the routing process and a search-and-repair process. Manually adjusting routes to pass over the hardmacros is time consuming and susceptible to human mistakes.
Referring to FIG. 1, a block diagram of a conventional layout for a circuit 10, including a conventional hardmacro 12, is shown. The hardmacro 12 includes a route guide (i.e., boundary 14) for all physical layers that blocks automatic routing across the hardmacro 12 on any layer. The route guide 14 causes the vertical and horizontal routes to go around the hardmacro. For example, a horizontally oriented network (i.e., NET 1) is routed up a left side, across a top side and down a right side of the hardmacro 12 due to the route guide 14. A vertically oriented network (e.g., NET 2) is routed left along a bottom side, up the left side, and right along the top side of the hardmacro 12 due to the route guide 14. A third network (i.e., NET 3) is routed right along the bottom side and up along the right side of the hardmacro 12. Routing around the hardmacro 12 can cause timing problems due to lengthy wires and congestion (i.e., region 20) where the networks NET 1 and NET 2 are in close proximity.